The present invention is related to the field of clock distribution circuits.
For analog-to-digital converters (ADCs) supporting high analog input frequencies, jitter on the sampling clock limits the signal-to-noise ratio (SNR) that can be achieved. In a typical ADC, the sampling clock is generated from an external or internal clock source and routed to a sampling switch forming part of the ADC. The clock distribution circuit typically includes a series of inverters that (a) route the clock to the sampling switch, and (b) provide sufficient drive required for the sampling switch. The power supply of the inverters in a clock distribution circuit can have significant noise, which produces jitter in the inverter's output signal. This jitter is a significant part of the total jitter appearing on the clock signal that ultimately drives the sampling switch.
Normally, inverters are designed with either layout considerations (area minimization) or drive considerations in mind. When layout considerations predominate, it is common to see the ratio of the widths of the two PMOS and NMOS devices that make up the inverter to be on the order of 1 (that is, Wp/Wn=1). When drive considerations predominate, a ratio of 3 to 4 is more common, which is substantially the inverse of the ratio of the majority carrier mobilities in the two devices. It is common to see device size ratios of 3 to 4 in the inverters used for clock distribution in ADCs and other analog integrated circuits.
Existing techniques to address the issue of noise-induced jitter include (a) reducing supply noise by using a low-inductance package, and (b) reducing switching noise that is coupled into the supply. Low-inductance packages have the undesirable drawback of higher cost. Furthermore, it can be difficult to reduce switching noise to the required degree. In all integrated circuits, there is always a power-noise trade-off, so reducing switching noise may mean that some other noise contribution is likely to increase.
It would be desirable to reduce the jitter in clocks such as used for sampling in ADCs without increasing other noise contributions and without requiring an unduly expensive package.